Design of high performance 8 bit binary multiplier using vedic multiplication algorithm with 16 nm technology

Vedic mathematics is a system of ancient Indian mathematics, which has a unique technique of solutions based on only 16 sutras or formulae. This technique is very useful for performing tedious mathematical operations at a very fast rate. Motivated by this ancient mathematical system, a high speed lo...

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Veröffentlicht in:	2017 1st International Conference on Electronics, Materials Engineering and Nano-Technology (IEMENTech) S. 1 - 5
Hauptverfasser:	Dey, Koyel, Chattopadhyay, Sudipta
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.04.2017
Schlagworte:	16 nm technology 65 nm technology Adders Algorithm design and analysis Delays Image coding McCMOS technology Simulation Urdhva Tiryakbhyam sutra Vedic multiplier
Online-Zugang:	Volltext
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