MMSE-QR factorization systolic array design for applications in MIMO signal detections

Complex-valued QR factorization is a fundamental but computationally intensive operation commonly used in various MIMO signal detection algorithms. In this paper, a novel factorization scheme based on Givens rotations and symmetrical nullification was devised. The proposed scheme successfully integr...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:2010 IEEE International Symposium on Circuits and Systems (ISCAS) s. 4181 - 4184
Hlavní autori: Yin-Tsung Hwang, Wei-Da Chen
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.05.2010
Predmet:
Bit error rate
Clocks
Computer architecture
Hardware
MIMO
Signal design
Signal detection
Symmetric matrices
Systolic arrays
Table lookup
ISBN:1424453089, 9781424453085
ISSN:0271-4302
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:Complex-valued QR factorization is a fundamental but computationally intensive operation commonly used in various MIMO signal detection algorithms. In this paper, a novel factorization scheme based on Givens rotations and symmetrical nullification was devised. The proposed scheme successfully integrates the MMSE criterion into factorization and can achieve better BER performance. Instead of working on a complex-valued domain, the scheme starts with a block-wise symmetric real-valued matrix counterpart. By exploiting the symmetrical property, the proposed scheme effectively reduced almost half of the computing complexity. Based on the presented scheme, a novel systolic array design featuring fully parallel and deeply pipelined processing was developed subject to the EWC 802.11n recommendation. Architecture optimization measures such as look-up table (LUT) free CORDIC implementations and hardware sharing among scaling operations were employed to minimize the hardware design complexity. Post layout simulation results using TSMC 0.18μm process indicate the proposed design, with a gate count of 233K and a maximum clock rate of 120 MHz, can admit a new 4×4 complex matrix for MMSE based factorization in every 8 clock cycles (66.7ns).
ISBN:1424453089
9781424453085
ISSN:0271-4302
DOI:10.1109/ISCAS.2010.5537597