An efficient methodology for transaction-level design of multi-core h.264 video decoder

H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallel...

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Bibliographic Details
Published in:2011 IEEE International Conference on Consumer Electronics (ICCE) pp. 399 - 400
Main Authors: Bingbing Xia, Fei Qiao, Huazhong Yang, Hui Wang
Format: Conference Proceeding
Language:English
Published: IEEE 01.01.2011
Subjects:
Analytical models
Decoding
Design methodology
Multicore processing
Parallel programming
Time domain analysis
Time varying systems
ISBN:9781424487110, 1424487110
ISSN:2158-3994
Online Access:Get full text
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Summary:H.264 video decoder is a good choice for embedded instruments because of its higher compression ratio than MPEG2, as well as its higher requirements of run-time computational resource. Multi-core system is the future of the embedded processor design for its power efficiency and multi-thread parallelization, and can be used to fit well with the requirements for this decoder. To simulate and evaluate the performance of such application-specific multi-core systems effectively, a method based on the combination of TLM language (SystemC) and shared-memory parallel programming model (OpenMP) is given, and experiments show that it can effectively simulate the system in a short time and more importantly, it can be used to help analyze the efficiency of each task-parallelization strategy. After optimization, the speedup ratio for each slice decoding can get about 3.06 on average under 4-core multi-core systems.
ISBN:9781424487110
1424487110
ISSN:2158-3994
DOI:10.1109/ICCE.2011.5722648