Efficient Reed-Solomon decoder with adaptive error-correcting capability

Reed-Solomon (RS) codes are widely used as error-correcting codes in digital communication and storage systems. This paper proposes an efficient architecture for RS decoder with adaptive error-correcting capability. This decoder can be employed to enable complexity-performance tradeoff and ensure da...

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Vydané v:The 19th Annual Wireless and Optical Communications Conference (WOCC 2010) s. 1 - 4
Hlavní autori: Jiangli Zhu, Xinmiao Zhang
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.05.2010
Predmet:
Adaptive error-correcting capability
Algebraic soft-decision decoding
Decoding
Delay
Digital communication
Hard-decision decoding
Hardware
Interpolation
Low-complexity Chase
Polynomials
Reed-Solomon codes
Testing
Time-varying channels
Variable speed drives
VLSI design
ISBN:142447597X, 9781424475971
ISSN:2379-1268
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Shrnutí:Reed-Solomon (RS) codes are widely used as error-correcting codes in digital communication and storage systems. This paper proposes an efficient architecture for RS decoder with adaptive error-correcting capability. This decoder can be employed to enable complexity-performance tradeoff and ensure data reliability in applications with time-varying channel condition, such as wireless communications. Specifically, the proposed decoder adopts the low-complexity Chase (LCC) algebraic soft-decision decoding algorithm. This algorithm tests 2 η vectors, and larger η leads to higher error-correcting capability. The proposed decoder is capable of implementing LCC decoding with variable η. In addition, the decoder hardware units are reused to incorporate hard-decision decoding (HDD). Detailed hardware requirement and latency analysis is provided for a (255, 239) RS code. Compared to the LCC decoder for η = 3 only, the adaptive RS decoder that can take care of both the HDD and LCC decoding with η ∈ {3, 4, 5} only has 1% area overhead.
ISBN:142447597X
9781424475971
ISSN:2379-1268
DOI:10.1109/WOCC.2010.5510637