A novel VHDL-based computer architecture design methodology

There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulati...

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Vydáno v:Rapid System Prototyping, 3rd International Workshop (RSP '92) s. 292 - 300
Hlavní autoři: MacDonald, R., Srinivasan, S., Williams, R., Aylor, J.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE Comput. Soc. Press 1992
Témata:
Circuit simulation
Computational modeling
Computer architecture
Design automation
Design methodology
Digital systems
Performance analysis
Petri nets
Process design
Queueing analysis
ISBN:0818635207, 9780818635205
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Abstract There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.< >
AbstractList There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The single path design methodology presented is a possible solution to this problem. The basic concept of the methodology is the use of one simulation language, the VHSIC hardware description language (VHDL, Version 1076) for all phases of design. The VHDL framework allows for iterative stepwise refinement of a model. A performance (uninterpreted) model can be refined to a register transfer level (RTL) description without changing modeling environments or completely rewriting the models. As an example, the performance-modeling phase of the single path design methodology is applied to the WM machine, a superscalar computer architecture.< >
Author Williams, R.
MacDonald, R.
Srinivasan, S.
Aylor, J.
Author_xml – sequence: 1
  givenname: R.
  surname: MacDonald
  fullname: MacDonald, R.
  organization: Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
– sequence: 2
  givenname: S.
  surname: Srinivasan
  fullname: Srinivasan, S.
  organization: Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
– sequence: 3
  givenname: R.
  surname: Williams
  fullname: Williams, R.
  organization: Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
– sequence: 4
  givenname: J.
  surname: Aylor
  fullname: Aylor, J.
  organization: Dept. of Electr. Eng., Virginia Univ., Charlottesville, VA, USA
BookMark eNotj9FKwzAUQAMq6OY-QJ_yA603Sdvk4tOYzg0Kig59HGlys1XaZrSdsL9XmOflvB04E3bZxY4YuxOQCgH4sP56_3hLBaJMZaYM4gWbgBGmULkEfc1mw_ANf2SZRIAb9jjnXfyhhn-unsqksgN57mJ7OI7Uc9u7fT2SG489cU9Dvet4S-M--tjE3emWXQXbDDT795Rtls-bxSopX1_Wi3mZ1AbHBFUgKSmrAE0RSIcCnHdaFrm2Eq0ICnJPAE6jdrIgSRbAW2EEBARZqSm7P2drItoe-rq1_Wl7vlO_hy5HOw
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/IWRSP.1992.243899
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Proceedings Order Plan All Online (POP All Online) 1998-present by volume
IEEE Xplore All Conference Proceedings
IEEE Xplore
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEEE Xplore
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EndPage 300
ExternalDocumentID 243899
GroupedDBID 6IE
6IK
6IL
AAJGR
AAWTH
ACGHX
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
OCL
RIE
RIL
ID FETCH-LOGICAL-i89t-93fe22e4b0986fe7f60cdc72657a29a1f305de00c797c26e2ea00da1810f902b3
IEDL.DBID RIE
ISBN 0818635207
9780818635205
IngestDate Tue Aug 26 16:44:31 EDT 2025
IsPeerReviewed false
IsScholarly false
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i89t-93fe22e4b0986fe7f60cdc72657a29a1f305de00c797c26e2ea00da1810f902b3
PageCount 9
ParticipantIDs ieee_primary_243899
PublicationCentury 1900
PublicationDate 19920000
PublicationDateYYYYMMDD 1992-01-01
PublicationDate_xml – year: 1992
  text: 19920000
PublicationDecade 1990
PublicationTitle Rapid System Prototyping, 3rd International Workshop (RSP '92)
PublicationTitleAbbrev IWRSP
PublicationYear 1992
Publisher IEEE Comput. Soc. Press
Publisher_xml – name: IEEE Comput. Soc. Press
SSID ssj0000442900
Score 1.2196901
Snippet There is a need for a design methodology that allows the representation and simulation of a design at various levels of abstraction and interpretation. The...
SourceID ieee
SourceType Publisher
StartPage 292
SubjectTerms Circuit simulation
Computational modeling
Computer architecture
Design automation
Design methodology
Digital systems
Performance analysis
Petri nets
Process design
Queueing analysis
Title A novel VHDL-based computer architecture design methodology
URI https://ieeexplore.ieee.org/document/243899
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEA22ePDkV8VvcvCaNpvNJhs8iVoqSFm0aG9lk0ygIFup2_5-k-xaFbx4S3IIE0Lyhpl58xC6MplkITtEjPeJCLcgSKkNJ6CFBO8f2Yy7KDYhx-N8OlVF22c7cmEAIBafQT8MYy7fLswqhMoGLEh1qw7qSCkaqtYmnEK5_1gpjR0ek9yjqLeg7a_zNc_apGZC1eDh9em5CEw91m82_SWuErFluPsvq_ZQ75ujh4sN-uyjLagO0fUNrhZreMMvo7tHEhDKYtPqNuCfOQNsY-UGbgSkY2i9hybD-8ntiLTyCGSeq5qo1AFjwDVVuXAgnaDGGslEJkumysT5l2yBUiOVNEwAg5JSW3pEp05RptMj1K0WFRwjnEijhco5aF5yJ4x3GQ1XOrEQiLRJeoIOwrFn700DjFlz4tM_V8_QTlPRGqIU56hbL1dwgbbNup5_LC_jpX0CmwmUdQ
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1NSwMxEA1aBT35VfHbHLymzabZZIMnUUuLtRQt2lvZJBMoyFZq299vkl2rghdvSQ5hhhDeMDNvHkJXJpUsVIeI8TER4RYEybXhBLSQ4OMjm3IXxSZkv5-NRmpQzdmOXBgAiM1n0AjLWMu3U7MIqbImC1Ldah1tpJwzWpK1VgkV6s8UpXHGY5J5HPU2VBN2vvZpVdZMqGp2X5-eB4Grxxrltb_kVSK6tHf-Zdcuqn-z9PBghT97aA2KA3R9g4vpEt7wS-euRwJGWWwq5Qb8s2qAbezdwKWEdEyu19GwfT-87ZBKIIFMMjUnquWAMeCaqkw4kE5QY41kIpU5U3ni_F-2QKmRShomgEFOqc09plOnKNOtQ1QrpgUcIZxIo4XKOGiecyeMDxoNVzqxEKi0SesY7Qe3x-_lCIxx6fHJn6eXaKszfOyNe93-wynaLvtbQ87iDNXmswWco02znE8-ZhfxAT8BifaXvA
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Rapid+System+Prototyping%2C+3rd+International+Workshop+%28RSP+%2792%29&rft.atitle=A+novel+VHDL-based+computer+architecture+design+methodology&rft.au=MacDonald%2C+R.&rft.au=Srinivasan%2C+S.&rft.au=Williams%2C+R.&rft.au=Aylor%2C+J.&rft.date=1992-01-01&rft.pub=IEEE+Comput.+Soc.+Press&rft.isbn=9780818635205&rft.spage=292&rft.epage=300&rft_id=info:doi/10.1109%2FIWRSP.1992.243899&rft.externalDocID=243899
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9780818635205/lc.gif&client=summon&freeimage=true
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9780818635205/mc.gif&client=summon&freeimage=true
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9780818635205/sc.gif&client=summon&freeimage=true