Stream-interleaved pipelined RISC processor design for SIMD and MIMD system development

Architectures exploiting time and space parallelism can be used to increase performance. Reduced instruction set computers (RISC) enhance performance of a single instruction stream through a simple load/store architecture. Data dependencies are eliminated by introducing NOP instructions in the strea...

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Bibliographische Detailangaben

Veröffentlicht in:	1993 (25th) Southeastern Symposium on System Theory S. 452 - 456
Hauptverfasser:	Killeen, T., Celenk, M.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 1993
Schlagworte:	Computer aided instruction Computer architecture Interleaved codes Multitasking Parallel processing Pipeline processing Process design Reduced instruction set computing Registers Very large scale integration
ISBN:	0818635606, 9780818635601
ISSN:	0094-2898
Online-Zugang:	Volltext
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