Reducing overheads in distributed shared memory systems

Shared memory machines have two major overheads: keeping caches coherent and managing the multiple threads of computation which enable tolerance of very long memory latencies. Thetis is a hybrid architecture providing both shared memory and efficient message passing; it will be built from 'comm...

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Veröffentlicht in:Proceedings of the Thirtieth Hawaii International Conference on System Sciences Jg. 1; S. 244 - 252 vol.1
Hauptverfasser: Morris, J., Gregg, R.R., Herbert, D., McCoull, J.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 1997
Schlagworte:
Access protocols
Coherence
Computer science
Costs
Delay
Field programmable gate arrays
Hardware
Memory management
Parallel programming
Yarn
ISBN:0818677430, 9780818677434
ISSN:1060-3425
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Zusammenfassung:Shared memory machines have two major overheads: keeping caches coherent and managing the multiple threads of computation which enable tolerance of very long memory latencies. Thetis is a hybrid architecture providing both shared memory and efficient message passing; it will be built from 'commodity' components and consists of sites with a small number of computation processors and a separate, programmable, auxiliary processor. The auxiliary processor performs overhead tasks, e.g. maintenance of cache directories, management of memory and thread queues; placed on its own bus, it does not block or delay memory accesses from computation processors which are not waiting for it. We describe how the use of a threaded variant of C (which has a functional style) enables the run-time system to dynamically determine coherence needs-dramatically reducing the overhead of maintaining coherent caches in a shared memory machine.
ISBN:0818677430
9780818677434
ISSN:1060-3425
DOI:10.1109/HICSS.1997.667263