Multialphabet arithmetic coding at 16 MBytes/sec

The design and performance of a nonadaptive hardware system for data compression by arithmetic coding are presented. The alphabet of the data source is the full 256-symbol ASCII character set, plus a non-ASCII end-of-file symbol. The key ideas are the non-arithmetic representation of the current int...

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Veröffentlicht in:Data Compression Conference S. 128 - 137
Hauptverfasser: Printz, H., Stubley, P.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE Comput. Soc. Press 1993
Schlagworte:
Circuit testing
Coprocessors
Data compression
Difference equations
Digital arithmetic
Field programmable gate arrays
Hardware
Laboratories
Registers
System testing
ISBN:9780818633928, 0818633921
Online-Zugang:Volltext
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Zusammenfassung:The design and performance of a nonadaptive hardware system for data compression by arithmetic coding are presented. The alphabet of the data source is the full 256-symbol ASCII character set, plus a non-ASCII end-of-file symbol. The key ideas are the non-arithmetic representation of the current interval width, which yields improved coding efficiency in the interval width update, and the design of a circuit for the code point update, which operates at a high speed independent of the length of the code point register. On a reconfigurable coprocessor, constructed from commercially available field-programmable gate arrays and static RAM, implementation compresses its input stream at better than 16 MBytes/sec.< >
ISBN:9780818633928
0818633921
DOI:10.1109/DCC.1993.253137