Low-Bit Precision Neural Network Architecture with High Immunity to Variability and Random Telegraph Noise based on Resistive Memories

In-memory computing architectures based on Resistive random access memory technologies (RRAM) are a promising candidate for the development of ultra-low power hardware accelerators that could enable the deployment of deep neural networks inference algorithms on energy constrained devices at the edge...

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Bibliographic Details

Published in:	IEEE International Reliability Physics Symposium proceedings pp. 1 - 6
Main Authors:	Zanotti, Tommaso, Puglisi, Francesco Maria, Pavan, Paolo
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.03.2021
Subjects:	Analytical models BNN Brain modeling Compact Modeling Computer architecture Data models Hardware Resistance Resistive RAM RRAM RTN
ISSN:	1938-1891
Online Access:	Get full text
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