Real-time FPGA architecture of modified Stable Euler-Number algorithm for image binarization

The stable Euler-Number based image binarization gives excellent visual results for video frames containing high amount of image noise. Being computationally expensive, its implementations are limited to general purpose processors for the most cost-effective solution or in application specific integ...

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Bibliographic Details
Published in:2009 16th IEEE International Conference on Image Processing (ICIP) pp. 3253 - 3256
Main Authors: Abbasi, N., Athow, J., Amer, A.
Format: Conference Proceeding
Language:English
Published: IEEE 01.11.2009
Subjects:
Algorithm design and analysis
Application specific integrated circuits
Computer architecture
Coprocessors
Field programmable gate arrays
FPGA
Gray-scale
Hardware
Image binarization
Image converters
Integrated circuit noise
Pipelined architecture
Real-time
Runtime
Stable Euler Number
ISBN:9781424456536, 1424456533
ISSN:1522-4880
Online Access:Get full text
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Summary:The stable Euler-Number based image binarization gives excellent visual results for video frames containing high amount of image noise. Being computationally expensive, its implementations are limited to general purpose processors for the most cost-effective solution or in application specific integrated circuits for maximum performance. This paper proposes a modified stable Euler-number based algorithm for image binarization and its real-time hardware implementation in a field programmable gate array with a pipelined architecture. The end result is a design that out-performs known software implementations while keeping the amount of noisy pixels introduced during the binarization process to a minimum. The hardware implementation results show that the proposed architecture gives accurate results compared to the software implementation.
ISBN:9781424456536
1424456533
ISSN:1522-4880
DOI:10.1109/ICIP.2009.5413985