Design space exploration of FPGA-based Deep Convolutional Neural Networks

Deep Convolutional Neural Networks (DCNN) have proven to be very effective in many pattern recognition applications, such as image classification and speech recognition. Due to their computational complexity, DCNNs demand implementations that utilize custom hardware accelerators to meet performance...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Veröffentlicht in:Proceedings of the ASP-DAC ... Asia and South Pacific Design Automation Conference S. 575 - 580
Hauptverfasser: Motamedi, Mohammad, Gysel, Philipp, Akella, Venkatesh, Ghiasi, Soheil
Format: Tagungsbericht Journal Article
Sprache:Englisch
Veröffentlicht: IEEE 01.01.2016
Schlagworte:
Accelerators
Computer architecture
Computer simulation
Convolution
Design analysis
Design engineering
Field programmable gate arrays
Kernel
Mathematical model
Mathematical models
Neural networks
Parallel processing
Platforms
Space exploration
ISSN:2153-697X
Online-Zugang:Volltext
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
Beschreibung
Zusammenfassung:Deep Convolutional Neural Networks (DCNN) have proven to be very effective in many pattern recognition applications, such as image classification and speech recognition. Due to their computational complexity, DCNNs demand implementations that utilize custom hardware accelerators to meet performance and energy-efficiency constraints. In this paper we propose an FPGA-based accelerator architecture which leverages all sources of parallelism in DCNNs. We develop analytical feasibility and performance estimation models that take into account various design and platform parameters. We also present a design space exploration algorithm for obtaining the implementation with the highest performance on a given platform. Simulation results with a real-life DCNN demonstrate that our accelerator outperforms other competing approaches, which disregard some sources of parallelism in the application. Most notably, our accelerator runs 1.9× faster than the state-of-the-art DCNN accelerator on the same FPGA device.
Bibliographie:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
ObjectType-Feature-3
content type line 23
SourceType-Conference Papers & Proceedings-2
ISSN:2153-697X
DOI:10.1109/ASPDAC.2016.7428073