Synthesis and Simulation of FPGA Based Hardware Design of RC4 Stream Cipher

This paper is focused on the synthesis and simulation of RC4 algorithm, which can be implemented on FPGA. A variable length key from 1 to 16 bytes is used by RC4 algorithm to initialize a 256-byte array. The subsequent pseudo-random bytes are generated by using this 256-byte array which is then gene...

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Vydané v:	Proceedings (International Confernce on Computational Intelligence and Communication Networks) s. 1177 - 1182
Hlavní autori:	Sonawane, Pradeep J., Bhadade, Umesh S.
Médium:	Konferenčný príspevok.. Journal Article
Jazyk:	English
Vydavateľské údaje:	IEEE 01.12.2015
Predmet:	Algorithms Arrays Ciphers Ciphertext Computer simulation Encryption Field programmable gate arrays Generators Hardware key scheduling algorithm plaintext pseudorandom number generation Software Software algorithms Synthesis Texts
ISSN:	2472-7555
On-line prístup:	Získať plný text
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