Invited Paper: VerilogEval: Evaluating Large Language Models for Verilog Code Generation

The increasing popularity of large language models (LLMs) has paved the way for their application in diverse domains. This paper proposes a benchmarking framework tailored specifically for evaluating LLM performance in the context of Verilog code generation for hardware design and verification. We p...

Full description

Bibliographic Details

Published in:	Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 1 - 8
Main Authors:	Liu, Mingjie, Pinckney, Nathaniel, Khailany, Brucek, Ren, Haoxing
Format:	Conference Proceeding
Language:	English
Published:	IEEE 28.10.2023
Subjects:	Benchmark testing Codes Combinational circuits Design automation Distance measurement Hardware Hardware design languages
ISSN:	1558-2434
Online Access:	Get full text
Tags:	Add Tag No Tags, Be the first to tag this record!