FPGA Hardware Design for Plenoptic 3D Image Processing Algorithm Targeting a Mobile Application

Over the past years, widespread use of applications based on 3D image processing has increased rapidly. It is being employed in various fields, such as research, medicine and automation. Plenoptic camera system is used to capture light-field that can be exploited to estimate the 3D depth of the scen...

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Vydané v:Proceedings of the ... IEEE International Conference on Acoustics, Speech and Signal Processing (1998) s. 7863 - 7867
Hlavní autori: Bhatti, Faraz, Greiner, Thomas
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 06.06.2021
Predmet:
3D image processing
Cameras
Estimation
FPGA hardware and optimizations
Graphics processing units
Hardware
Image processing
light-field camera
Plenoptic camera
Signal processing algorithms
Three-dimensional displays
ISSN:2379-190X
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Popis
Shrnutí:Over the past years, widespread use of applications based on 3D image processing has increased rapidly. It is being employed in various fields, such as research, medicine and automation. Plenoptic camera system is used to capture light-field that can be exploited to estimate the 3D depth of the scene. The respective algorithms consist of a large number of computation-intensive instructions. It eventually leads to the problem of large execution time of the algorithm. Moreover, they require substantial amount of memory cells for the storage of intermediate and final results. Desktop GPU based solutions are power intensive and therefore cannot be used in the mobile applications with low energy requirements. The idea presented in this paper is to use the FPGA based hardware design to improve the performance of a 3D depth estimation algorithm by utilizing the advantage of concurrent execution. The algorithm is implemented, evaluated and the results show that FPGA design reduces the respective execution time significantly.
ISSN:2379-190X
DOI:10.1109/ICASSP39728.2021.9414690