VHDL Compiler with Natural Parallel Comands Execution
The paper considers the process of compilers designing and highlight parallelism in algorithmic structures. The advantages of existing solutions in the hardware and software areas are highlighted and a new approach for creating a software and hardware compiler is designed. The requirements for our l...
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| Vydáno v: | IEEE EUROCON 2021 - 19th International Conference on Smart Technologies s. 331 - 337 |
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| Hlavní autoři: | , , , , |
| Médium: | Konferenční příspěvek |
| Jazyk: | angličtina |
| Vydáno: |
IEEE
06.07.2021
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| Témata: | |
| On-line přístup: | Získat plný text |
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| Shrnutí: | The paper considers the process of compilers designing and highlight parallelism in algorithmic structures. The advantages of existing solutions in the hardware and software areas are highlighted and a new approach for creating a software and hardware compiler is designed. The requirements for our language and the peculiarities of the functioning of each component of the compiler were clearly defined. The basis of the alphabet consists of Latin upper and lower case characters, numbers and delimiters. A description of the lexical analyzer, which highlights tokens and keywords in the text of the input program is provided. Syntactic rules of language (structure of constructions) in the form of diagrams of the Bekus-Naur form and semantic requirements concerning identifiers, length of names of identifiers and labels, arithmetic operations and input/output ports are described as well. The processor compiler with natural parallel execution of instructions was developed. Performance testing and comparative analysis of the efficiency of the developed compiler has shown the advantages of the created solution. |
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| DOI: | 10.1109/EUROCON52738.2021.9535606 |