Advanced Encryption Standard for embedded applications: An FPGA-based implementation using VHDL

Computing systems are ubiquitous in today's world and hence security has become a seminal factor that should be given more priority along with other parameters. In this context, many cryptographic systems have been emerged of which Advanced Encryption Standard (AES) has been furnished as one of...

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Vydáno v:2021 3rd IEEE Middle East and North Africa COMMunications Conference (MENACOMM) s. 120 - 124
Hlavní autoři: Rabbi Emon, Md Arefin, Jamil Apon, Hasan, Faisal, Fahim, Nishat, Mirza Muntasir, Adil Morshed, Khandakar, Al Naser, Ahmed Mujtaba, Zerin Jaba, Fatema, Anzum, Fariha
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 03.12.2021
Témata:
AES
Conferences
Cryptography
Decryption
Encryption
FPGA
Hardware
Simulation
Software
Throughput
VHDL
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Shrnutí:Computing systems are ubiquitous in today's world and hence security has become a seminal factor that should be given more priority along with other parameters. In this context, many cryptographic systems have been emerged of which Advanced Encryption Standard (AES) has been furnished as one of the most prevalent security algorithms now-a-days with a view to fighting against data security as well as ensuring end-to-end secure communication. Moreover, Field-programmable gate array (FPGA) is a reprogrammable device which can be an intriguing option for hardware implementations. This paper implements AES encryption and decryption on FPGA using VHDL (VHSIC Hardware Description Language) in ModelSim software. The design process employs iterative looping having block and key size of 128 bits and takes help from an S-box lookup table implementation. Later on, all the simulation results along with the calculation of latency and throughput have been presented. The S-box computation has been done in such a way so that it reduces the latency and gives low complexity architecture of the hardware implementation.
DOI:10.1109/MENACOMM50742.2021.9678241