High Speed Floating Point Multiply Accumulate Unit using Offset Binary Coding

This paper deals with less delay efficient multiplier and accumulator unit for inner product, filtering [3] applications, convolution, image and video processing applications etc., Multiply and Accumulate unit plays and important role in Digital signal processor. On designing this consumes large are...

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Vydané v:2020 7th International Conference on Smart Structures and Systems (ICSSS) s. 1 - 5
Hlavní autori: Lahari, P.L., Bharathi, M., Shirur, Yasha Jyothi M
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.07.2020
Predmet:
Adders
Conferences
Delays
Distributed Arithmetic
Encoding
floating point
Floating-point arithmetic
Multiply Accumulate Unit
Offset binary coding
Read only memory
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Shrnutí:This paper deals with less delay efficient multiplier and accumulator unit for inner product, filtering [3] applications, convolution, image and video processing applications etc., Multiply and Accumulate unit plays and important role in Digital signal processor. On designing this consumes large area because it contains partial products so Distributed Arithmetic is considered to improve the speed but for each added input size of the ROM increases exponentially so offset binary coding preferred. By using floating point Offset binary coding complete speed of the processor will be increased. These designs are simulated and synthesized with Xilinx 14.7 ISE software. It achieves best area and less delay result when compared with other designs.
DOI:10.1109/ICSSS49621.2020.9202333