High Speed Floating Point Multiply Accumulate Unit using Offset Binary Coding

This paper deals with less delay efficient multiplier and accumulator unit for inner product, filtering [3] applications, convolution, image and video processing applications etc., Multiply and Accumulate unit plays and important role in Digital signal processor. On designing this consumes large are...

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Veröffentlicht in:	2020 7th International Conference on Smart Structures and Systems (ICSSS) S. 1 - 5
Hauptverfasser:	Lahari, P.L., Bharathi, M., Shirur, Yasha Jyothi M
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.07.2020
Schlagworte:	Adders Conferences Delays Distributed Arithmetic Encoding floating point Floating-point arithmetic Multiply Accumulate Unit Offset binary coding Read only memory
Online-Zugang:	Volltext
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