A Novel Approach for Measurement Throughput Maximization in FPGA-based TDCs

This paper presents a new approach for dead-time minimization while preserving low resource usage and high resolution in FPGA-based time-to-digital (TDC) converters. The proposed TDC architecture can be employed in applications in which many events need to be detected in a short time, such as time-o...

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Veröffentlicht in:2021 7th International Conference on Event-Based Control, Communication, and Signal Processing (EBCCSP) S. 1 - 6
Hauptverfasser: Parsakordasiabi, Mojtaba, Vornicu, Ion, Rodriguez-Vazquez, Angel, Carmona-Galan, Ricardo
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 22.06.2021
Schlagworte:
Delay lines
field-programmable gate array (FPGA)
measurement throughput
Minimization
multichannel TDCs
Positron emission tomography
Signal processing
Size measurement
Throughput
Time-frequency analysis
time-of-flight (ToF)
time-to-digital converter (TDC)
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Zusammenfassung:This paper presents a new approach for dead-time minimization while preserving low resource usage and high resolution in FPGA-based time-to-digital (TDC) converters. The proposed TDC architecture can be employed in applications in which many events need to be detected in a short time, such as time-of-flight positron emission tomography (ToF-PET) applications. The presented architecture consists of a toggling input stage, a tapped delay line (TDL), a dual-mode counter-based encoder, a coarse counter, and a bin width calibration stage. The minimum dead-time of TDL TDCs is two clock cycles. The proposed architecture reduced dead-time to one clock cycle. The measurement results of the proposed low-resources TDC in an Artix-7 FPGA show [-0.80, 1.34] LSB differential nonlinearity (DNL) and [-0.73, 1.97] LSB integral non-linearity (INL). The measured LSB size and single-shot precision (SSP) are 22.1 ps and 28.43 ps, respectively.
DOI:10.1109/EBCCSP53293.2021.9502401