TITAC-2: an asynchronous 32-bit microprocessor based on scalable-delay-insensitive model

Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-perf...

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Veröffentlicht in:Proceedings International Conference on Computer Design VLSI in Computers and Processors S. 288 - 294
Hauptverfasser: Takamura, A., Kuwako, M., Imai, M., Fujii, T., Ozawa, M., Fukasaku, I., Ueno, Y., Nanya, T.
Format: Tagungsbericht
Sprache:Englisch
Japanisch
Veröffentlicht: IEEE 22.11.2002
Schlagworte:
Circuits
Clocks
CMOS technology
Delay effects
Delay systems
Information science
Microprocessors
Very large scale integration
Wire
Wiring
ISBN:9780818682063, 081868206X
ISSN:1063-6404
Online-Zugang:Volltext
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Zusammenfassung:Asynchronous design has a potential of solving many difficulties, such as clock skew and power consumption, which synchronous counterpart suffers with current and future VLSI technologies. This paper proposes a new delay model, the scalable-delay-insensitive (SDI) model, for dependable and high-performance asynchronous VLSI system design. Then, based on the SDI model, the paper presents the design, chip implementation, and evaluation results of a 32-bit asynchronous microprocessor TITAC-2 whose instruction set is based on the MIPS R2000. The measured performance of TITAC-2 is 52.3 MIPS using the Dhrystone V2.1 benchmark.
ISBN:9780818682063
081868206X
ISSN:1063-6404
DOI:10.1109/ICCD.1997.628881