Citáce podľa APA (7th ed.)

Kolagatla, V. R., Raveendran, A., & Desalphine, V. (2024, September). A Novel and Efficient SPI enabled RSA Crypto Accelerator for Real-Time applications. International Symposium on VLSI Design and Test, 1-6. https://doi.org/10.1109/VDAT63601.2024.10705738

Citácia podle Chicago (17th ed.)

Kolagatla, Venkata Reddy, Aneesh Raveendran, a Vivian Desalphine. "A Novel and Efficient SPI Enabled RSA Crypto Accelerator for Real-Time Applications." International Symposium on VLSI Design and Test Sep. 2024: 1-6. https://doi.org/10.1109/VDAT63601.2024.10705738.

Citácia podľa MLA (8th ed.)

Kolagatla, Venkata Reddy, et al. "A Novel and Efficient SPI Enabled RSA Crypto Accelerator for Real-Time Applications." International Symposium on VLSI Design and Test, Sep. 2024, pp. 1-6, https://doi.org/10.1109/VDAT63601.2024.10705738.

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