AMARETTO: Enabling Efficient Quantum Algorithm Emulation on Low-Tier FPGAs

Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to the limitations of current quantum devices. Software simulators are time and memory-consuming, making hardware emulators an attract...

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Vydáno v:Proceedings of the ... IEEE International Conference on Electronics, Circuits, and Systems (Online) s. 1 - 4
Hlavní autoři: Conti, Christian, Volpe, Deborah, Graziano, Mariagrazia, Zamboni, Maurizio, Turvani, Giovanna
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 18.11.2024
Témata:
Computer architecture
Emulation
Field Programmable Gate Array
Field programmable gate arrays
Hardware
Industries
Logic gates
Quan-tum Computing Simulation
Quantum algorithm
Quantum Algorithm Verification
Quantum Computing Emulation
Qubit
Software
Vectors
ISSN:2995-0589
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Shrnutí:Researchers and industries are increasingly drawn to quantum computing for its computational potential. However, validating new quantum algorithms is challenging due to the limitations of current quantum devices. Software simulators are time and memory-consuming, making hardware emulators an attractive alternative. This article introduces AMARETTO (quAntuM ARchitecture EmulaTion TechnOlogy), designed for quantum computing emulation on low-tier Field-Programmable gate arrays (FPGAs), supporting Clifford+T and rotational gate sets. It simplifies and accelerates the verification of quantum algorithms using a Reduced-Instruction-Set-Computer (RISC)-like structure and efficient handling of sparse quantum gates. A dedicated compiler translates OpenQASM 2.0 into RISC-like instructions. AMARETTO is validated against the Qiskit simulators. Our results show successful emulation of sixteen qubits on a AMD Kria KV260 SoM. This approach rivals other works in emulated qubit capacity on a smaller, more affordable FPGA.
ISSN:2995-0589
DOI:10.1109/ICECS61496.2024.10848965