Fully Convolution Based Denoise Autoencoder AI Accelerator for ECG Arrhythmia Classification

The electrocardiogram (ECG) is a reliable indicator for arrhythmias detection. This paper introduces an arrhythmia classification system designed for identifying cardiovascular diseases, following the international standards presented by the Association for the Advancement of Medical Instrumentation...

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Bibliographic Details
Published in:Biomedical Circuits and Systems Conference pp. 1 - 5
Main Authors: Wu, Yu-Chun, Jhang, Bo-Yu, Lee, Shuenn-Yuh, Chen, Ju-Yi
Format: Conference Proceeding
Language:English
Published: IEEE 24.10.2024
Subjects:
Accuracy
AI Accelerator
Arrhythmia
Data models
Denoise Autoencoder
Electrocardiography
Fully Convolution Neural Network
Noise reduction
Power demand
Semiconductor device modeling
Testing
Training
ISSN:2766-4465
Online Access:Get full text
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Summary:The electrocardiogram (ECG) is a reliable indicator for arrhythmias detection. This paper introduces an arrhythmia classification system designed for identifying cardiovascular diseases, following the international standards presented by the Association for the Advancement of Medical Instrumentation (AAMI). Arrhythmic conditions are categorized into five major classes. The proposed deep learning accelerator (DLA) combines noise reduction and disease classification features to enhance accuracy. The noise reduction process utilizes a fully convolutional denoising autoencoder (DAE) model that reconstructs clean ECG data. The denoising performance, measured by signal-to-noise ratio (SNR), reaches 20.19 dB. By applying transfer learning, the encoder of DAE is integrated with the R-peak interval model through model fusion, enabling the simultaneous learning of single-window ECG features and long-term heart rate variations. To validate the model's robustness, test data from the MIT-BIH and AHA databases were randomly selected before model training. Ultimately, the model achieves 97.8% accuracy in blind testing. Additionally, this study presents an AI accelerator implemented using Taiwan Semiconductor Manufacturing Company (TSMC) 180-nm CMOS technology. The accelerator incorporates dynamic zero-gating process elements, reducing power consumption by up to 55.8%. The chip utilizes 14 KB of static random-access memory (SRAM), three FIFO data buffers, and eight processing elements, each with three MACs. The total power consumption is 0.533 mW, and the accelerator achieves inference in just 55 ms.
ISSN:2766-4465
DOI:10.1109/BioCAS61083.2024.10798155