Combined Split Manufacturing and Logic Obfuscation Based on Emerging Technologies at High Level for Secure 3D IC Design

Split Manufacturing (SM) and Logic Obfuscation (LO) are potent design-for-trust solutions to mitigate hardware security threats when fabricating Integrated Circuits (ICs) at untrusted foundries. However, many such defense methods are subject to attacks such as Network Flow Attack and Boolean Satisfi...

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Vydáno v:Conference proceedings : Midwest Symposium on Circuits and Systems s. 1403 - 1407
Hlavní autoři: Chakraborty, Haimanti, Vemuri, Ranga
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 11.08.2024
Témata:
3D Integrated Circuits
Circuits and systems
Emerging Technologies (Polymorphic Switch Boxes)
Foundries
Hardware security
Hardware Security at High Level
Logic
Logic Obfuscation
Manufacturing
Split Manufacturing
Switches
Three-dimensional displays
ISSN:1558-3899
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Shrnutí:Split Manufacturing (SM) and Logic Obfuscation (LO) are potent design-for-trust solutions to mitigate hardware security threats when fabricating Integrated Circuits (ICs) at untrusted foundries. However, many such defense methods are subject to attacks such as Network Flow Attack and Boolean Satisfiability Attack, that have attempted to reconstruct the missing BEOL (Back End Of Line) signals and decrypt the design. Hence, it is crucial to select BEOL signals carefully. Although several defense strategies have been proposed to protect the design against the attacks, many have been implemented at lower abstraction levels that incur expensive re-synthesis cycles. In this paper, we combine SM and LO for enhanced security of 3D ICs by proposing a BEOL signal selection method at high level based on assigning edge-weights to prioritize Data Flow Graph edges, that also identify locations for Polymorphic Switch Boxes (PSBs) for LO. A PSB has more key-bit combinations compared to a CMOS SB for an attacker to correctly unlock it. Our method decreases attack correctness with increase in the percentage of edges lifted and has minimal impact on design performance in terms of area and wirelength.
ISSN:1558-3899
DOI:10.1109/MWSCAS60917.2024.10658909