High performance VLSI implementation of Context-based Adaptive Variable Length Coding (CAVLC) for H.264 encoder

The video coding standard H.264 uses Context-based Adaptive Variable Length Coding (CAVLC) as one of its entropy encoding techniques. This paper proposes VLSI architecture for CAVLC algorithm. The designed hardware meets the required speed of H.264 without compromising the hardware cost. The CAVLC e...

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Vydáno v:2013 Fourth National Conference on Computer Vision, Pattern Recognition, Image Processing and Graphics (NCVPRIPG) s. 1 - 4
Hlavní autoři: Mukherjee, R., Mahajan, V., Chakrabarti, I., Sengupta, S.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.12.2013
Témata:
CAVLC
Encoding
Field programmable gate arrays
FPGA
H.264
Hardware
LUT
Read only memory
Table lookup
Video coding
VLSI
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Shrnutí:The video coding standard H.264 uses Context-based Adaptive Variable Length Coding (CAVLC) as one of its entropy encoding techniques. This paper proposes VLSI architecture for CAVLC algorithm. The designed hardware meets the required speed of H.264 without compromising the hardware cost. The CAVLC encoder works at a maximum clock frequency of 126 MHz when implemented in Xilinx 10.1i, Virtex-5 technology. The speed is quite appreciable when compared to other existing works. The implemented architecture meets the required rate for processing of HD-1080 format video sequence.
DOI:10.1109/NCVPRIPG.2013.6776186