MAGNet: A Modular Accelerator Generator for Neural Networks
Deep neural networks have been adopted in a wide range of application domains, leading to high demand for inference accelerators. However, the high cost associated with ASIC hardware design makes it challenging to build custom accelerators for different targets. To lower design cost, we propose MAGN...
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| Published in: | Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design pp. 1 - 8 |
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| Main Authors: | , , , , , , , , , , , , , , , |
| Format: | Conference Proceeding |
| Language: | English |
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IEEE
01.11.2019
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| ISSN: | 1558-2434 |
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| Abstract | Deep neural networks have been adopted in a wide range of application domains, leading to high demand for inference accelerators. However, the high cost associated with ASIC hardware design makes it challenging to build custom accelerators for different targets. To lower design cost, we propose MAGNet, a modular accelerator generator for neural networks. MAGNet takes a target application consisting of one or more neural networks along with hardware constraints as input and produces synthesizable RTL for a neural network accelerator ASIC as well as valid mappings for running the target networks on the generated hardware. MAGNet consists of three key components: (i) MAGNet Designer, a highly configurable architectural template designed in C++ and synthesizable by high-level synthesis tools. MAGNet Designer supports a wide range of design-time parameters such as different data formats, diverse memory hierarchies, and dataflows. (ii) MAGNet Mapper, an automated framework for exploring different software mappings for executing a neural network on the generated hardware. (iii) MAGNet Tuner, a design space exploration framework encompassing the designer, the mapper, and a deep learning framework to enable fast design space exploration and co-optimization of architecture and application. We demonstrate the utility of MAGNet by designing an inference accelerator optimized for image classification application using three different neural networks-AlexNet, ResNet, and DriveNet. MAGNet-generated hardware is highly efficient and leverages a novel multi-level dataflow to achieve 40 fJ/op and 2.8 TOPS/mm 2 in a 16nm technology node for the ResNet-50 benchmark with <1% accuracy loss on the ImageNet dataset. |
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| AbstractList | Deep neural networks have been adopted in a wide range of application domains, leading to high demand for inference accelerators. However, the high cost associated with ASIC hardware design makes it challenging to build custom accelerators for different targets. To lower design cost, we propose MAGNet, a modular accelerator generator for neural networks. MAGNet takes a target application consisting of one or more neural networks along with hardware constraints as input and produces synthesizable RTL for a neural network accelerator ASIC as well as valid mappings for running the target networks on the generated hardware. MAGNet consists of three key components: (i) MAGNet Designer, a highly configurable architectural template designed in C++ and synthesizable by high-level synthesis tools. MAGNet Designer supports a wide range of design-time parameters such as different data formats, diverse memory hierarchies, and dataflows. (ii) MAGNet Mapper, an automated framework for exploring different software mappings for executing a neural network on the generated hardware. (iii) MAGNet Tuner, a design space exploration framework encompassing the designer, the mapper, and a deep learning framework to enable fast design space exploration and co-optimization of architecture and application. We demonstrate the utility of MAGNet by designing an inference accelerator optimized for image classification application using three different neural networks-AlexNet, ResNet, and DriveNet. MAGNet-generated hardware is highly efficient and leverages a novel multi-level dataflow to achieve 40 fJ/op and 2.8 TOPS/mm 2 in a 16nm technology node for the ResNet-50 benchmark with <1% accuracy loss on the ImageNet dataset. |
| Author | Pinckney, Nathaniel Keller, Ben Khailany, Brucek Zhang, Yanqing Zimmer, Brian Fojtik, Matthew Emer, Joel Shao, Yakun Sophia Dai, Steve Raina, Priyanka Venkatesan, Rangharajan Clemons, Jason Klinefelter, Alicia Keckler, Stephen W. Wang, Miaorong Dally, William J. |
| Author_xml | – sequence: 1 givenname: Rangharajan surname: Venkatesan fullname: Venkatesan, Rangharajan organization: NVIDIA – sequence: 2 givenname: Yakun Sophia surname: Shao fullname: Shao, Yakun Sophia organization: NVIDIA – sequence: 3 givenname: Miaorong surname: Wang fullname: Wang, Miaorong organization: Massachusetts Institute of Technology – sequence: 4 givenname: Jason surname: Clemons fullname: Clemons, Jason organization: NVIDIA – sequence: 5 givenname: Steve surname: Dai fullname: Dai, Steve organization: NVIDIA – sequence: 6 givenname: Matthew surname: Fojtik fullname: Fojtik, Matthew organization: NVIDIA – sequence: 7 givenname: Ben surname: Keller fullname: Keller, Ben organization: NVIDIA – sequence: 8 givenname: Alicia surname: Klinefelter fullname: Klinefelter, Alicia organization: NVIDIA – sequence: 9 givenname: Nathaniel surname: Pinckney fullname: Pinckney, Nathaniel organization: NVIDIA – sequence: 10 givenname: Priyanka surname: Raina fullname: Raina, Priyanka organization: Stanford University – sequence: 11 givenname: Yanqing surname: Zhang fullname: Zhang, Yanqing organization: NVIDIA – sequence: 12 givenname: Brian surname: Zimmer fullname: Zimmer, Brian organization: NVIDIA – sequence: 13 givenname: William J. surname: Dally fullname: Dally, William J. organization: Stanford University – sequence: 14 givenname: Joel surname: Emer fullname: Emer, Joel organization: Massachusetts Institute of Technology – sequence: 15 givenname: Stephen W. surname: Keckler fullname: Keckler, Stephen W. organization: NVIDIA – sequence: 16 givenname: Brucek surname: Khailany fullname: Khailany, Brucek organization: NVIDIA |
| BookMark | eNotj8FOwzAQRA0Cibb0CziQH0jxru3YhlMUIFRqywXOlROvpUBIkJMK8fdEIoeZ904jzZJddH1HjN0C3wBwe7ctivxRKg12g3wqYyUC6jO2ttqARgMoFLfnbAFKmRSlkFdsOQwfnCNHky3Ywz4vDzTeJ3my7_2pdTHJ65paim7sY1JSN1uYcqBTdO2E8aePn8M1uwyuHWg9c8Xen5_eipd091pui3yXNqDVmAbrpHfgK58FLipZZbbmUpBHH2oiH4wMQSlAJ3nlfaWNwSzjSqEOhA7Eit387zZEdPyOzZeLv8f5q_gDAUJKxg |
| ContentType | Conference Proceeding |
| DBID | 6IE 6IH CBEJK RIE RIO |
| DOI | 10.1109/ICCAD45719.2019.8942127 |
| DatabaseName | IEEE Electronic Library (IEL) Conference Proceedings IEEE Proceedings Order Plan (POP) 1998-present by volume IEEE Xplore All Conference Proceedings IEEE Electronic Library (IEL) IEEE Proceedings Order Plans (POP) 1998-present |
| DatabaseTitleList | |
| Database_xml | – sequence: 1 dbid: RIE name: IEEE Electronic Library (IEL) url: https://ieeexplore.ieee.org/ sourceTypes: Publisher |
| DeliveryMethod | fulltext_linktorsrc |
| Discipline | Engineering |
| EISBN | 9781728123509 172812350X |
| EISSN | 1558-2434 |
| EndPage | 8 |
| ExternalDocumentID | 8942127 |
| Genre | orig-research |
| GroupedDBID | 123 6IE 6IF 6IH 6IL 6IN AAWTH ABLEC ADZIZ ALMA_UNASSIGNED_HOLDINGS APO BEFXN BFFAM BGNUA BKEBE BPEOZ CBEJK CHZPO FEDTE IEGSK IJVOP M43 OCL RIE RIL RIO |
| ID | FETCH-LOGICAL-i175t-f9a4da1dbd6f03b4b69c043ed2dfceedf84ff5512a40bddb78826605527fe2a13 |
| IEDL.DBID | RIE |
| ISICitedReferencesCount | 82 |
| ISICitedReferencesURI | http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000524676400085&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| IngestDate | Wed Aug 27 07:43:05 EDT 2025 |
| IsPeerReviewed | false |
| IsScholarly | true |
| Language | English |
| LinkModel | DirectLink |
| MergedId | FETCHMERGED-LOGICAL-i175t-f9a4da1dbd6f03b4b69c043ed2dfceedf84ff5512a40bddb78826605527fe2a13 |
| PageCount | 8 |
| ParticipantIDs | ieee_primary_8942127 |
| PublicationCentury | 2000 |
| PublicationDate | 2019-Nov. |
| PublicationDateYYYYMMDD | 2019-11-01 |
| PublicationDate_xml | – month: 11 year: 2019 text: 2019-Nov. |
| PublicationDecade | 2010 |
| PublicationTitle | Digest of technical papers - IEEE/ACM International Conference on Computer-Aided Design |
| PublicationTitleAbbrev | ICCAD |
| PublicationYear | 2019 |
| Publisher | IEEE |
| Publisher_xml | – name: IEEE |
| SSID | ssj0020286 |
| Score | 2.4903557 |
| Snippet | Deep neural networks have been adopted in a wide range of application domains, leading to high demand for inference accelerators. However, the high cost... |
| SourceID | ieee |
| SourceType | Publisher |
| StartPage | 1 |
| SubjectTerms | Accelerator magnets Computer architecture Costs Generators Hardware Magnetic domains Magnetic resonance imaging Neural networks Space exploration Tuners |
| Title | MAGNet: A Modular Accelerator Generator for Neural Networks |
| URI | https://ieeexplore.ieee.org/document/8942127 |
| WOSCitedRecordID | wos000524676400085&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D |
| hasFullText | 1 |
| inHoldings | 1 |
| isFullTextHit | |
| isPrint | |
| link | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV07T8MwED61FQMsPFrEWx4YCc3DtWOYqooCQ6sOIHWrYvssVUJt1ab8fs5OVEBiYUnOkaIkZ0Wfz3ffdwC3aWqFJZyIjBZZxJ3ASFlFViIwFRKlQB2aTcjxOJ9O1aQBdzsuDCKG4jO892bI5dul2fqtsm6ufP5SNqEppay4WrvginBS1PVbSay6rwP6Et6TiSej0KG-9VcPlQAhw8P_PfwIOt9cPDbZocwxNHBxAgc_ZATb8DjqP4-xfGB9NlpaX1fK-sYQnoQUOquUpb1FC1Tm1TiKDzqF8u9NB96HT2-Dl6huihDNCenLyKmC2yKx2goXZ5proUzMM7Spdf5VXM6do2VQWvBYW6spxCUMjr3QmsO0SLJTaC2WCzwDllNwZyVm2KM_xem84ATnmNnU0MgYcw5t74bZqtK9mNUeuPj78iXse09XPL0raJXrLV7Dnvks55v1TZisLzzNlak |
| linkProvider | IEEE |
| linkToHtml | http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV1LS8NAEB5qFdSLjyq-3YNHY_PYbhI9lWJtsQ09VOitZHdnoSCttKm_39lNqApevCSzgZBklvDt7Mz3DcBdGGqhCSc8JUXkcSPQS3VKViAwFDHGAqVrNhFnWTKZpKMa3G-4MIjois_wwZoul68Xam23yppJavOX8RZstzhZJVtrE14RUoqqgivw02a_Q9_CW3Fg6Sh0qG7-1UXFgUj34H-PP4STbzYeG21w5ghqOD-G_R9Cgg14GrZfMiweWZsNF9pWlrK2UoQoLonOSm1pa9ESlVk9jvydTq4AfHUCb93ncafnVW0RvBlhfeGZNOc6D7TUwviR5FKkyucR6lAb-yom4cbQQijMuS-1lhTkEgr7VmrNYJgH0SnU54s5ngFLKLzTMUbYon_FyCTnBOgY6VDRSCl1Dg3rhulHqXwxrTxw8fflW9jtjYeD6aCfvV7CnvV6ydq7gnqxXOM17KjPYrZa3riJ-wI27Jjw |
| openUrl | ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=Digest+of+technical+papers+-+IEEE%2FACM+International+Conference+on+Computer-Aided+Design&rft.atitle=MAGNet%3A+A+Modular+Accelerator+Generator+for+Neural+Networks&rft.au=Venkatesan%2C+Rangharajan&rft.au=Shao%2C+Yakun+Sophia&rft.au=Wang%2C+Miaorong&rft.au=Clemons%2C+Jason&rft.date=2019-11-01&rft.pub=IEEE&rft.eissn=1558-2434&rft.spage=1&rft.epage=8&rft_id=info:doi/10.1109%2FICCAD45719.2019.8942127&rft.externalDocID=8942127 |