System-Level Retiming and Pipelining

In this paper, we examine retiming and pipelining in the context of system-level optimization techniques. Our main contributions are: (a) functionally equivalent retiming and delay balancing as necessary techniques for pipelining and retiming system-level graphs while maintaining numerical fidelity,...

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Bibliographic Details

Published in:	2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines pp. 80 - 87
Main Authors:	Venkataramani, Girish, Yongfeng Gu
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.05.2014
Subjects:	Algorithm design and analysis Delays Hardware design languages high-level synthesis ESL pipelining retiming multi-cycle Simulink HDL Coder MATLAB Pipeline processing Registers Software packages
Online Access:	Get full text
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