Multi-layer parallel decoding algorithm and vlsi architecture for quasi-cyclic LDPC codes

We propose a multi-layer parallel decoding algorithm and VLSI architecture for decoding of structured quasi-cyclic low-density parity-check codes. In the conventional layered decoding algorithm, the block-rows of the parity check matrix are processed sequentially, or layer after layer. The maximum n...

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Bibliographic Details

Published in:	2011 IEEE International Symposium of Circuits and Systems (ISCAS) pp. 1776 - 1779
Main Authors:	Yang Sun, Guohui Wang, Cavallaro, J. R.
Format:	Conference Proceeding
Language:	English
Published:	IEEE 01.05.2011
Subjects:	Decoding IEEE 802.11n Standard Parallel processing Parity check codes Registers Throughput Very large scale integration
ISBN:	1424494737, 9781424494736
ISSN:	0271-4302
Online Access:	Get full text
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