Efficient Write Scheme for Algorithm-Based Multi-Ported Memory

This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In t...

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Vydáno v:Proceedings of Technical Program of International Symposium on VLSI Design, Automation and Test s. 1 - 4
Hlavní autoři: Bo-Ya Chen, Bo-En Chen, Bo-Cheng Lai
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.04.2019
Témata:
Banking
Memory management
Memory modules
Registers
SRAM cells
ISSN:2472-9124
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Shrnutí:This paper proposes REMAP+, a novel design that enables efficient write scheme for algorithmic multi-ported memory, and attains better performance with smaller area. REMAP+ applies the banking structure of memory design and implements the remap table with SRAM cells instead of costly registers. In the remap table, REMAP+ only keeps the most significant bit of write addresses to more efficiently utilize the space in the table. The hash write controller is simplified with the first fit algorithm to handle write conflict with shorter latency. REMAP+ is implemented in a pipeline scheme to further increase the processing throughput. For a 3W1R memory with 16K depth, REMAP+ has attained 22% shorter access latency and 31.3% smaller area when compared with the previous design.
ISSN:2472-9124
DOI:10.1109/VLSI-DAT.2019.8741927