FPGA Implementation of the Bilinear Interpolation Algorithm for Image Demosaicking

Current image sensors offer a raw output that incorporates a bayer color filter pattern, and additional processing is required to obtain a full color image. This paper presents a bilinear interpolation algorithm to demosaick images with bayer color pattern; the algorithm is implemented in a single f...

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Vydáno v:2009 International Conference on Electrical, Communications, and Computers s. 25 - 28
Hlavní autoři: Fuentes, Ivan Olaf Hernandez, Bravo-Zanoguera, Miguel Enrique, Yanez, Guillermo Galaviz
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.02.2009
Témata:
Application software
Bilinear Interpolation
Communication system control
Field programmable gate arrays
FPGA
Interpolation
Organizing
Pipelined processing
Power electronics
Power engineering and energy
Process control
Robots
Signal processing
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Shrnutí:Current image sensors offer a raw output that incorporates a bayer color filter pattern, and additional processing is required to obtain a full color image. This paper presents a bilinear interpolation algorithm to demosaick images with bayer color pattern; the algorithm is implemented in a single field programmable gate array (FPGA) device using a pipelined architecture. A comparison between images obtained with the FGPA-based interpolation and a software-based interpolation using Matlab demosaicking function is presented. The proposed FPGA demosaick algorithm achieves reasonable image quality, and it is an economic alternative for smart camera devices.
DOI:10.1109/CONIELECOMP.2009.47