Efficient memory optimization and high throughput decoding architecture based on LDPC codes

Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. Here, the memory bandwidth is the key performance limiting factor. And the decoding throughput of a LDPC decoder is limited by this memory bandwidth requ...

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Vydané v:2013 International Conference on Information Communication and Embedded Systems (ICICES) s. 731 - 734
Hlavní autori: Ngangom, L., Manikandan, V.
Médium: Konferenčný príspevok..
Jazyk:English
Vydavateľské údaje: IEEE 01.02.2013
Predmet:
Alignment
Decoding
Field programmable gate arrays
field programmable logic array (FPGA)
folding
low-density parity-check (LDPC) decoder
Memory management
memory system optimization
normalized min-sum algorithm
Parity check codes
quasi-cyclic low-density parity-check (QC-LDPC) codes
Random access memory
Throughput
Vectors
ISBN:9781467357869, 1467357863
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Shrnutí:Low-Density Parity-Check (LDPC) code is one kind of prominent error correcting codes (ECC) being considered in next generation industry standards. Here, the memory bandwidth is the key performance limiting factor. And the decoding throughput of a LDPC decoder is limited by this memory bandwidth requirement. The decoder implementation complexity has been the bottleneck of its application. This paper present a specific optimization called vectorization to take advantage of the configurable data-width and depth of embedded memory in an FPGA to improve the throughput of a decoder for quasicyclic LDPC codes. It is shown that this presented hardware structure will be highly competent in high throughput and low decoding latency applications.
ISBN:9781467357869
1467357863
DOI:10.1109/ICICES.2013.6508255