Citáce podľa APA (7th ed.)

Jiang, Q., Liu, J., & Hu, H. (2018, December). A Thread Modularity Approach for Verification Concurrent Software Based on Abstract Interpretation. 2018 25th Asia-Pacific Software Engineering Conference (APSEC), 119-128. https://doi.org/10.1109/APSEC.2018.00026

Citácia podle Chicago (17th ed.)

Jiang, Qingyu, Jing Liu, a Haodong Hu. "A Thread Modularity Approach for Verification Concurrent Software Based on Abstract Interpretation." 2018 25th Asia-Pacific Software Engineering Conference (APSEC) Dec. 2018: 119-128. https://doi.org/10.1109/APSEC.2018.00026.

Citácia podľa MLA (8th ed.)

Jiang, Qingyu, et al. "A Thread Modularity Approach for Verification Concurrent Software Based on Abstract Interpretation." 2018 25th Asia-Pacific Software Engineering Conference (APSEC), Dec. 2018, pp. 119-128, https://doi.org/10.1109/APSEC.2018.00026.

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