Design methodologies and circuit optimization techniques for low power CMOS VLSI design

Low power is the real test for late hardware businesses. Control scattering is an essential thought as far as execution and area for VLSI Chip outline. Control administration procedures are for the most part used to configuration low power circuits and frameworks. Insights demonstrate that 40% or co...

Celý popis

Podrobná bibliografia

Vydané v:	2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI) s. 1759 - 1763
Hlavní autori:	Geetha, B. T., Padmavathi, B., Perumal, V.
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 01.09.2017
Predmet:	Clock gating Dynamic power lector method etc Power consumption VLSI
ISBN:	9781538608135, 1538608138
On-line prístup:	Získať plný text
Tagy:	Pridať tag Žiadne tagy, Buďte prvý, kto otaguje tento záznam!