Design methodologies and circuit optimization techniques for low power CMOS VLSI design

Low power is the real test for late hardware businesses. Control scattering is an essential thought as far as execution and area for VLSI Chip outline. Control administration procedures are for the most part used to configuration low power circuits and frameworks. Insights demonstrate that 40% or co...

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Veröffentlicht in:	2017 IEEE International Conference on Power, Control, Signals and Instrumentation Engineering (ICPCSI) S. 1759 - 1763
Hauptverfasser:	Geetha, B. T., Padmavathi, B., Perumal, V.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 01.09.2017
Schlagworte:	Clock gating Dynamic power lector method etc Power consumption VLSI
ISBN:	9781538608135, 1538608138
Online-Zugang:	Volltext
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