A self-testing and calibration technique for current-steering DACs

In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing alg...

Celý popis

Uloženo v:
Podrobná bibliografie
Vydáno v:2008 International Symposiium on VLSI Design, Automation and Test s. 295 - 298
Hlavní autoři: Yuan-Lang Ma, Jiun-Lang Huang
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 01.04.2008
Témata:
Built-in self-test
Calibration
Circuit testing
Decoding
Digital signal processing
Digital-analog conversion
Fuses
Prototypes
Signal processing algorithms
Voltage
ISBN:1424416167, 9781424416165
On-line přístup:Získat plný text
Tagy: Přidat tag
Žádné tagy, Buďte první, kdo vytvoří štítek k tomuto záznamu!
Abstract In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 mum technology. The measurement results show that INL, DNL, and SFDR are significantly improved.
AbstractList In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and an analog comparator is added to facilitate self-testing and calibration. In self- testing mode, the controller executes the self-testing algorithm to characterize the DAC higher bits and computes the calibration information. In function mode, it produces the inputs to the duplicated lower bits for calibration. To validate the idea, a 14-bit prototype has been fabricated using TSMC 0.35 mum technology. The measurement results show that INL, DNL, and SFDR are significantly improved.
Author Jiun-Lang Huang
Yuan-Lang Ma
Author_xml – sequence: 1
  surname: Yuan-Lang Ma
  fullname: Yuan-Lang Ma
  organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
– sequence: 2
  surname: Jiun-Lang Huang
  fullname: Jiun-Lang Huang
  organization: Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei
BookMark eNpFUM1OwzAYC4JJ0LEHQFzyAi1J89tj6caPNInL4Dql6RcIKikk2YG3p4hJ-GJbsizLBToLUwCEriipKCXNzcu63VU1Ibrigtdc0RNU0FlwKqkSp_9GqgUq5qBqiGgIO0erlN7JDC4YE-QC3bY4wejKDCn78IpNGLA1o--jyX4KOIN9C_7rANhNEdtDjBBymTJA_I2v2y5dooUzY4LVkZfo-W6z6x7K7dP9Y9duSz9vyqWSzvWDkZorMziqLXE9tdA7aftBS2mdNoNu1KAaqmsnjKCm4dZxxoyQjrEluv7r9QCw_4z-w8Tv_fEA9gMzIk8o
ContentType Conference Proceeding
DBID 6IE
6IL
CBEJK
RIE
RIL
DOI 10.1109/VDAT.2008.4542471
DatabaseName IEEE Electronic Library (IEL) Conference Proceedings
IEEE Xplore POP ALL
IEEE Xplore All Conference Proceedings
IEEE Electronic Library (IEL)
IEEE Proceedings Order Plans (POP All) 1998-Present
DatabaseTitleList
Database_xml – sequence: 1
  dbid: RIE
  name: IEL
  url: https://ieeexplore.ieee.org/
  sourceTypes: Publisher
DeliveryMethod fulltext_linktorsrc
EISBN 1424416175
9781424416172
EndPage 298
ExternalDocumentID 4542471
Genre orig-research
GroupedDBID 6IE
6IF
6IK
6IL
6IN
AAJGR
AARBI
AAWTH
ALMA_UNASSIGNED_HOLDINGS
BEFXN
BFFAM
BGNUA
BKEBE
BPEOZ
CBEJK
IERZE
OCL
RIE
RIL
ID FETCH-LOGICAL-i175t-76ffbda6847adf18c0fb1cebf6cbd866cf8ad897d79182f5a51a94cf433a56f33
IEDL.DBID RIE
ISBN 1424416167
9781424416165
ISICitedReferencesCount 3
ISICitedReferencesURI http://www.webofscience.com/api/gateway?GWVersion=2&SrcApp=Summon&SrcAuth=ProQuest&DestLinkType=CitingArticles&DestApp=WOS_CPL&KeyUT=000256565800073&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
IngestDate Wed Aug 27 02:10:41 EDT 2025
IsPeerReviewed false
IsScholarly false
LCCN 2007905903
Language English
LinkModel DirectLink
MergedId FETCHMERGED-LOGICAL-i175t-76ffbda6847adf18c0fb1cebf6cbd866cf8ad897d79182f5a51a94cf433a56f33
PageCount 4
ParticipantIDs ieee_primary_4542471
PublicationCentury 2000
PublicationDate 2008-April
PublicationDateYYYYMMDD 2008-04-01
PublicationDate_xml – month: 04
  year: 2008
  text: 2008-April
PublicationDecade 2000
PublicationTitle 2008 International Symposiium on VLSI Design, Automation and Test
PublicationTitleAbbrev VDAT
PublicationYear 2008
Publisher IEEE
Publisher_xml – name: IEEE
SSID ssj0000453350
Score 1.410562
Snippet In this paper, a current-steering DAC self-testing and calibration technique is proposed. In the proposed scheme, the lower bits of the DAC are duplicated and...
SourceID ieee
SourceType Publisher
StartPage 295
SubjectTerms Built-in self-test
Calibration
Circuit testing
Decoding
Digital signal processing
Digital-analog conversion
Fuses
Prototypes
Signal processing algorithms
Voltage
Title A self-testing and calibration technique for current-steering DACs
URI https://ieeexplore.ieee.org/document/4542471
WOSCitedRecordID wos000256565800073&url=https%3A%2F%2Fcvtisr.summon.serialssolutions.com%2F%23%21%2Fsearch%3Fho%3Df%26include.ft.matches%3Dt%26l%3Dnull%26q%3D
hasFullText 1
inHoldings 1
isFullTextHit
isPrint
link http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV27TsMwFLVKxcAEqEW85YER07h-j6WlYkBVh4K6VX6iSihFTcr3YydpEBILm-MhinNknXuv7zkG4M4wElnIEOQCDjFBcQRpYRQaeh63Hs4MDhXSL2I2k8ulmnfAfauF8d5XzWf-IQ2rs3y3sbtUKhtQRoc0CcYPhOC1Vqutp8TQhBCW7bVbMZDhYm_p1Dyz5lQTZ2rwNhkt6k7K5qW_blepyGV6_L_POgH9H5UenLf8cwo6Pu-BxxEs_EdAZXLPyN-hzh2MMKSkOEEAW89WGKNVaGt3JhShriwJ4WQ0Lvrgdfq0GD-j5p4EtI7kXyLBQzBO80g0Ov5yabNgsPUmcGuc5NwGqZ1UwgkVs4nANMNaURsoIZrxQMgZ6Oab3J8DyGRMb4z1ET5G6dBp4aVhWtmAiRRKXoBeWv_qs7bCWDVLv_x7-goc1e0VqdHlGnTL7c7fgEP7Va6L7W2F3zfiFpgZ
linkProvider IEEE
linkToHtml http://cvtisr.summon.serialssolutions.com/2.0.0/link/0/eLvHCXMwlV3LTgIxFG0ImuhKDRjfduHSygx9LxElGJGwQMOO9GlIzGBg8PttZ4YxJm7czcyimfakOffe3nMKwI2mOLCQxsj61IcExWKkuJao61jYemmiU18gPeLjsZjN5KQBbmstjHOuaD5zd_GxOMu3S7OJpbIOoaRLomB8hxLSTUq1Vl1RCcEJxjTZqrdCKMP41tSpeqfVuWaayM7bQ29a9lJWw_66X6Wgl8HB_37sELR_dHpwUjPQEWi4rAXue3DtPjzKo39G9g5VZmEAIqbFEQRYu7bCEK9CU_ozoQB2YUoIH3r9dRu8Dh6n_SGqbkpAi0D_OeLMe20VC1SjwqILk3idGqc9M9oKxowXygrJLZchn_BU0VRJYjzBWFHmMT4GzWyZuRMAqQgJjjYuABgX2SruhKZKGp9iwaU4Ba04__lnaYYxr6Z-9vfna7A3nL6M5qOn8fM52C-bLWLbywVo5quNuwS75itfrFdXBZbfAC2bYA
openUrl ctx_ver=Z39.88-2004&ctx_enc=info%3Aofi%2Fenc%3AUTF-8&rfr_id=info%3Asid%2Fsummon.serialssolutions.com&rft_val_fmt=info%3Aofi%2Ffmt%3Akev%3Amtx%3Abook&rft.genre=proceeding&rft.title=2008+International+Symposiium+on+VLSI+Design%2C+Automation+and+Test&rft.atitle=A+self-testing+and+calibration+technique+for+current-steering+DACs&rft.au=Yuan-Lang+Ma&rft.au=Jiun-Lang+Huang&rft.date=2008-04-01&rft.pub=IEEE&rft.isbn=9781424416165&rft.spage=295&rft.epage=298&rft_id=info:doi/10.1109%2FVDAT.2008.4542471&rft.externalDocID=4542471
thumbnail_l http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424416165/lc.gif&client=summon&freeimage=true
thumbnail_m http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424416165/mc.gif&client=summon&freeimage=true
thumbnail_s http://covers-cdn.summon.serialssolutions.com/index.aspx?isbn=9781424416165/sc.gif&client=summon&freeimage=true