Design and Optimization of Self-Biased Complementary Folded Cascode

This paper presents design and optimization procedure of a self-biased complementary folded cascade. A self-biased scheme is chosen as a technique that saves power and circuit area, and is less sensitive to process variations. The gain of basic folded cascode is enhanced using a gain boosting approa...

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Vydané v:	MELECON 2006 - 2006 IEEE Mediterranean Electrotechnical Conference s. 145 - 148
Hlavní autori:	Ceperic, V., Butkovic, Z., Baric, A.
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 2006
Predmet:	Boosting Circuit simulation CMOS technology Cost function Design optimization Operational amplifiers Optimization methods Particle swarm optimization Power amplifiers Power supplies
ISBN:	9781424400874, 1424400872
ISSN:	2158-8473
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