Defect Tolerance in Nanotechnology Switches Using a Greedy Reconfiguration Algorithm

Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully cr...

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Veröffentlicht in:8th International Symposium on Quality Electronic Design (ISQED'07) S. 807 - 813
Hauptverfasser: Ramsundar, S., Ahmad Al-Yamani, Pradhan, D.K.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.03.2007
Schlagworte:
Fabrication
Frequency estimation
Lithography
Nanoscale devices
Nanotechnology
Nanowires
Polynomials
Self-assembly
Silicon
Switches
ISBN:0769527957, 9780769527956
ISSN:1948-3287
Online-Zugang:Volltext
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Zusammenfassung:Lithography based IC fabrication is rapidly approaching its limit in terms of feature size. The current alternative is nanotechnology based fabrication, which relies on self-assembly of nanotubes or nanowires. Such a process is subject to a high defect rate, which can be tolerated using carefully crafted defect tolerance techniques. This paper presents an algorithm for reconfiguration-based defect tolerance in nanotechnology switches. The algorithm offers an average switch density improvement of 50% to 100% to most recently published techniques
ISBN:0769527957
9780769527956
ISSN:1948-3287
DOI:10.1109/ISQED.2007.55