Parallel volume rendering on a single-chip SIMD architecture

Volume rendering has great potential for parallelization due to the tremendous number of computations necessary. Besides the enormous computational power needed, the memory interface is usually of crucial importance and frequently the bottleneck. The paper presents an implementation of a parallel ra...

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Vydané v:	IEEE Parallel and Large Data Visualization and Graphics Symposium 2001 s. 107 - 157
Hlavní autori:	Meissner, M., Grimm, S., Strasser, W., Packer, J., Latimer, D.
Médium:	Konferenčný príspevok..
Jazyk:	English
Vydavateľské údaje:	IEEE 2001
Predmet:	Casting Computer architecture Computer graphics Concurrent computing Interpolation Memory architecture Parallel processing Parallel programming Real time systems Rendering (computer graphics)
ISBN:	0780372239, 9780780372238
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