A current-mode approach to CMOS neural network implementation

CMOS equivalents of the synapse and the neuron are proposed for LSI implementation of an adaptive analog neural network. The synapse is a multiplying digital-to-analog converter based on an R-2R ladder and the neuron consists of the second-generation current conveyor. Prototype chips fabricated inde...

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Bibliographic Details
Published in:1997 3rd International Conference on Algorithms and Architectures for Parallel Processing : ICA³PP/97 : Melbourne, Australia, December 10-12, 1997 pp. 625 - 637
Main Authors: Watanabe, K., Wang, L., Cha, H.-W., Ogawa, S.
Format: Conference Proceeding
Language:English
Japanese
Published: IEEE 01.01.1997
Subjects:
Adaptive signal processing
Adaptive systems
CMOS process
Digital-analog conversion
Large scale integration
Neural networks
Neurons
Performance analysis
Prototypes
Wideband
ISBN:0780342291, 9780780342293
Online Access:Get full text
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Summary:CMOS equivalents of the synapse and the neuron are proposed for LSI implementation of an adaptive analog neural network. The synapse is a multiplying digital-to-analog converter based on an R-2R ladder and the neuron consists of the second-generation current conveyor. Prototype chips fabricated independently using 0.6 /spl mu/m CMOS process have confirmed the wideband signal processing capability owing to a fully current-mode approach. Detailed analyses of measured performances have also given the design criteria for fully parallel implementation.
ISBN:0780342291
9780780342293
DOI:10.1109/ICAPP.1997.651528