A current-mode approach to CMOS neural network implementation

CMOS equivalents of the synapse and the neuron are proposed for LSI implementation of an adaptive analog neural network. The synapse is a multiplying digital-to-analog converter based on an R-2R ladder and the neuron consists of the second-generation current conveyor. Prototype chips fabricated inde...

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Vydané v:	1997 3rd International Conference on Algorithms and Architectures for Parallel Processing : ICA³PP/97 : Melbourne, Australia, December 10-12, 1997 s. 625 - 637
Hlavní autori:	Watanabe, K., Wang, L., Cha, H.-W., Ogawa, S.
Médium:	Konferenčný príspevok..
Jazyk:	English Japanese
Vydavateľské údaje:	IEEE 01.01.1997
Predmet:	Adaptive signal processing Adaptive systems CMOS process Digital-analog conversion Large scale integration Neural networks Neurons Performance analysis Prototypes Wideband
ISBN:	0780342291, 9780780342293
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