APA (7th ed.) Citation

Watanabe, K., Wang, L., Cha, H., & Ogawa, S. (1997, January). A current-mode approach to CMOS neural network implementation. 1997 3rd International Conference on Algorithms and Architectures for Parallel Processing : ICA³PP/97 : Melbourne, Australia, December 10-12, 1997, 625-637. https://doi.org/10.1109/ICAPP.1997.651528

Chicago Style (17th ed.) Citation

Watanabe, K., L. Wang, H.-W Cha, and S. Ogawa. "A Current-mode Approach to CMOS Neural Network Implementation." 1997 3rd International Conference on Algorithms and Architectures for Parallel Processing : ICA³PP/97 : Melbourne, Australia, December 10-12, 1997 Jan. 1997: 625-637. https://doi.org/10.1109/ICAPP.1997.651528.

MLA (9th ed.) Citation

Watanabe, K., et al. "A Current-mode Approach to CMOS Neural Network Implementation." 1997 3rd International Conference on Algorithms and Architectures for Parallel Processing : ICA³PP/97 : Melbourne, Australia, December 10-12, 1997, Jan. 1997, pp. 625-637, https://doi.org/10.1109/ICAPP.1997.651528.