A global code scheduling technique using guarded PDG

For instruction-level parallel machines, it is essential to extract parallelly executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine...

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Veröffentlicht in:IEEE First ICA³PP, IEEE First International Conference on Algorithms and Architectures for Parallel Processing, Brisbane, Australia, 19-21 April, 1995 Jg. 2; S. 661 - 669 vol.2
Hauptverfasser: Koseki, A., Komatsu, H., Fukazawa, Y.
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 01.01.1995
Schlagworte:
Arithmetic
Computer aided instruction
Concurrent computing
Dynamic scheduling
Laboratories
Processor scheduling
ISBN:9780780320185, 0780320182
Online-Zugang:Volltext
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Beschreibung
Zusammenfassung:For instruction-level parallel machines, it is essential to extract parallelly executable instructions from a program by code scheduling. In this paper, we propose a new code scheduling technique using an extension of PDG. This technique parallelizes non-numerical programs, producing better machine codes than these created by percolation scheduling.< >
ISBN:9780780320185
0780320182
DOI:10.1109/ICAPP.1995.472253