A superparallel image filtering digital-pixel-sensor employing a compressive multiplication technique

A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to accelerate the processing speed. As a result, speed-ups from 3.2 to 5.2 were achieved for Gaussian kernels ranged from 5×5 to 15×15 in scale-invari...

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Bibliographic Details
Published in:2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS) pp. 363 - 366
Main Authors: Hongbo Zhu, Asada, Kunihiro
Format: Conference Proceeding
Language:English
Japanese
Published: IEEE 01.12.2014
Subjects:
Computer architecture
Feature extraction
Image coding
Image resolution
Kernel
Parallel processing
Random access memory
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Summary:A full-pixel parallel image filtering architecture is developed based on the digital-pixel-sensor. A compressive multiplication technique is employed to accelerate the processing speed. As a result, speed-ups from 3.2 to 5.2 were achieved for Gaussian kernels ranged from 5×5 to 15×15 in scale-invariant feature transform (SIFT) algorithm. A 108 × 96-pixel sensor was designed using a 0.18 μm CMOS process in a 5 mm×5 mm chip. By simulating the sensor at 100 MHz, the image filtering times for 5×5, 7×7, and 9×9 Gaussian kernels in the SIFT algorithm are 34 μs, 49 μs, and 83 μs, respectively. Such a high processing speed is very important for achieving the real-time performance when filtering high resolution images with large kernels.
DOI:10.1109/ICECS.2014.7049997