Control Scheme for a CGRA

Ability to instantiate low cost and agile FSMs that can implement an arbitrary parallelism and combine such FSMs in a chain and in a hierarchy is one of the key differentiating factors between the ASICs and MPSOCs. CGRAs that have been reported in literature, like MPSOCs, also lack this ASIC like ab...

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Bibliographic Details
Published in:2010 22nd International Symposium on Computer Architecture and High Performance Computing pp. 17 - 24
Main Authors: Shami, M A, Hemani, A
Format: Conference Proceeding
Language:English
Published: IEEE 01.10.2010
Subjects:
Application specific integrated circuits
CGRA
Delay
Dynamically Reprogrammable Resource Arrays
Field programmable gate arrays
Parallel processing
Program processors
Reconfigurable Architecture
Registers
Switches
ISBN:9781424482870, 1424482879
ISSN:1550-6533
Online Access:Get full text
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Summary:Ability to instantiate low cost and agile FSMs that can implement an arbitrary parallelism and combine such FSMs in a chain and in a hierarchy is one of the key differentiating factors between the ASICs and MPSOCs. CGRAs that have been reported in literature, like MPSOCs, also lack this ASIC like ability. The downside of ASICs is their lack of reuse and high engineering cost. We present a CGRA architecture that retains the programmability of CGRA and yet has the ASIC like ability to construct a) arbitrarily parallel data-path/FSM combine, b) chain an arbitrary number of such FSMs and c) create a hierarchy of such chains. We present in detail the architecture of such a control scheme and illustrate its use for an example composed of FFT and FIRs. We quantify the benefits of our approach by benchmarking for energy-delay product against a) ASICs (4.8X worse), b) a state-of-the-art CGRA (4.58X better) and FPGAs (63.95X better).
ISBN:9781424482870
1424482879
ISSN:1550-6533
DOI:10.1109/SBAC-PAD.2010.12