High throughput and resource efficient AES encryption/decryption for SANs

To secure the data stored in large-scale Storage Area Network (SAN) applications, high throughput Advanced Encryption Standard (AES) encryption and decryption are required. However, this solution may take up more hardware resources, which leads to unscalability for future needs. To solve this proble...

Celý popis

Uložené v:
Podrobná bibliografia
Vydané v:IEEE International Conference on Circuits and Systems (Online) s. 1166 - 1169
Hlavní autori: Wang, Yi, Ha, Yajun
Médium: Konferenčný príspevok.. Journal Article
Jazyk:English
Vydavateľské údaje: IEEE 01.05.2016
Predmet:
Digital signal processing
Encryption
Field programmable gate arrays
Hardware
Inverse
Mathematical analysis
Mathematical models
Storage area networks
Throughput
Transformations (mathematics)
ISSN:2379-447X
On-line prístup:Získať plný text
Tagy: Pridať tag
Žiadne tagy, Buďte prvý, kto otaguje tento záznam!
Popis
Shrnutí:To secure the data stored in large-scale Storage Area Network (SAN) applications, high throughput Advanced Encryption Standard (AES) encryption and decryption are required. However, this solution may take up more hardware resources, which leads to unscalability for future needs. To solve this problem, we develop a high throughput and resource efficient AES encryption/decryption based on FPGA, which fully exploiting the dedicated resources of modern FPGAs, such as Block RAM (BRAM) and Digital Signal Processing (DSP) slices. We also propose a unified architecture for AES encryption and decryption. Furthermore, we move the map and the inverse map functions outside the AES encryption/decryption round. In order to shorten the critical path, we optimized the transformation matrix of the map function and its inverse transformation matrix. We use the same hardware resource to perform computations of both SubBytes and InvSubBytes, as well as computations of MixColumns and InvMixColumns. Finally, proper pipelined registers and DSP slices have been inserted into the proposed unrolling architecture to achieve high throughput. Experimental results show that our designs can achieve 78.22 Gbits/s using 5613 slices, 144 DSP slices without BRAM; or 68.44 Gbits/s using 4345 slices, 171 DSP slices with 400X36K BRAMs on XC6VLX240T FPGA.
Bibliografia:ObjectType-Article-2
SourceType-Scholarly Journals-1
ObjectType-Conference-1
ObjectType-Feature-3
content type line 23
SourceType-Conference Papers & Proceedings-2
ISSN:2379-447X
DOI:10.1109/ISCAS.2016.7527453