Hameed, A. L., Akawee, M. M., & Hameed, M. (2022, December 27). Power Reduction using Pipeline-Clock Gating Technique in Synchronous Design with FPGA Implementation. 2022 3rd Information Technology To Enhance e-learning and Other Application (IT-ELA), 210-214. https://doi.org/10.1109/IT-ELA57378.2022.10107932
Chicago-Zitierstil (17. Ausg.)Hameed, Ahmed Lateef, Mustafa Mahmood Akawee, und Maan Hameed. "Power Reduction Using Pipeline-Clock Gating Technique in Synchronous Design with FPGA Implementation." 2022 3rd Information Technology To Enhance E-learning and Other Application (IT-ELA) 27 Dec. 2022: 210-214. https://doi.org/10.1109/IT-ELA57378.2022.10107932.
MLA-Zitierstil (9. Ausg.)Hameed, Ahmed Lateef, et al. "Power Reduction Using Pipeline-Clock Gating Technique in Synchronous Design with FPGA Implementation." 2022 3rd Information Technology To Enhance E-learning and Other Application (IT-ELA), 27 Dec. 2022, pp. 210-214, https://doi.org/10.1109/IT-ELA57378.2022.10107932.