Power Reduction using Pipeline-Clock Gating Technique in Synchronous Design with FPGA Implementation

The major drawback for compression process using Huffman design the overhead created from operation. Therefore, the most important way used to overcome these difficulties by clock gating procedure to make the system works in high performance and slow mode. Power dissipation includes two types of pow...

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Veröffentlicht in:2022 3rd Information Technology To Enhance e-learning and Other Application (IT-ELA) S. 210 - 214
Hauptverfasser: Hameed, Ahmed Lateef, Akawee, Mustafa Mahmood, Hameed, Maan
Format: Tagungsbericht
Sprache:Englisch
Veröffentlicht: IEEE 27.12.2022
Schlagworte:
Clock gating
Logic gates
Low Power Architecture
Optimal pipeline clocking
Pipeline
Pipelines
Power demand
Power dissipation
Real-time systems
Scalability
Switches
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Zusammenfassung:The major drawback for compression process using Huffman design the overhead created from operation. Therefore, the most important way used to overcome these difficulties by clock gating procedure to make the system works in high performance and slow mode. Power dissipation includes two types of power, dynamic power and static power. The last one is very small and the main effect of the total power consumption is generated from dynamic power. In this paper Huffman design with pipeline-clock gating technique (PIP-CG) using altera FPGA was implemented and simulated. The proposed method implements the term of transparent pipeline to modify the clock dissipated power by using the way of dynamically transparent pipeline registers. By improving a new control for pipeline transparent it can be implemented to any stages of pipeline. Decrease the overhead with the transparent way is also suggested to decrease applying overhead. Suggested gated-clock control logic is extended to pipeline collapsing. Power consumption for Huffman using PIP-CG was analyzed and simulated. In order to implement the design architectures, for ASIC implementation. Coding and decoding architectures were created using language of Verilog HDL Quartus II 11.1 in the Web Edition 32-Bit. Moreover, simulation process was achieved by utilizing ModelSim-Altera 10.0c with the Quartus II 11.1 Starter Edition.
DOI:10.1109/IT-ELA57378.2022.10107932