An Efficient FPGA Implementation of LDPC Decoder for 5G New Radio

In this work, we present a new design approach for the implementation of an efficient FPGA architecture for the Low-Density Parity Check codes (LDPC) Decoder according to the specifications of 5G New-Radio (NR) cellular communication standard, which has advantages such as high coding gain, good thro...

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Veröffentlicht in:	2023 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI) S. 1 - 5
Hauptverfasser:	Devi, R. Varshini, Rajaram, S.
Format:	Tagungsbericht
Sprache:	Englisch
Veröffentlicht:	IEEE 19.04.2023
Schlagworte:	5G New-Radio Decoding Field-Programmable Gate-Array (FPGA) Hardware HDL LDPC Decoder New Radio Normalized Min-Sum algorithm Parity check codes Table lookup Timing Verilog HDL Very large scale integration Wireless communication
Online-Zugang:	Volltext
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