An Efficient FPGA Implementation of LDPC Decoder for 5G New Radio

In this work, we present a new design approach for the implementation of an efficient FPGA architecture for the Low-Density Parity Check codes (LDPC) Decoder according to the specifications of 5G New-Radio (NR) cellular communication standard, which has advantages such as high coding gain, good thro...

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Vydáno v:2023 International Conference on Recent Advances in Electrical, Electronics, Ubiquitous Communication, and Computational Intelligence (RAEEUCCI) s. 1 - 5
Hlavní autoři: Devi, R. Varshini, Rajaram, S.
Médium: Konferenční příspěvek
Jazyk:angličtina
Vydáno: IEEE 19.04.2023
Témata:
5G New-Radio
Decoding
Field-Programmable Gate-Array (FPGA)
Hardware
HDL
LDPC Decoder
New Radio
Normalized Min-Sum algorithm
Parity check codes
Table lookup
Timing
Verilog HDL
Very large scale integration
Wireless communication
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Shrnutí:In this work, we present a new design approach for the implementation of an efficient FPGA architecture for the Low-Density Parity Check codes (LDPC) Decoder according to the specifications of 5G New-Radio (NR) cellular communication standard, which has advantages such as high coding gain, good throughput, and low power dissipation. The complexity and time required for implementing 5G NR LDPC decoders using conventional HDL-based methods can pose a significant challenge. To solve this problem, we presented a methodology that utilizes high-level modeling tools to design LDPC decoders for 5G, making the process more efficient. This approach can support the programmable logic design and be used for FPGA implementation. The methodology has been tested by designing, simulating, and implementing representative LDPC decoders. The 5G NR LDPC decoder realization is achieved using a Circular Shift-Register-based model to decrease the difficulty. The data is decoded using the Normalized Min-Sum algorithm. FPGA implementation analyzes the system productivity and efficiency with hardware utilization of the chip and the timing parameters summary. The VLSI circuit design of this Decoder is executed using Xilinx 14.1, programmed with Verilog HDL and hardware operation is evaluated on the Virtex-7 FPGA kit.
DOI:10.1109/RAEEUCCI57140.2023.10134365