Verification of Hardware Resource Utilization through High Level Synthesis for FPGA Implementation

Recently, there has been a sharp rise in demand for hardware implementations because of the improved accuracy of Convolutional Neural Networks (CNN) on a wide range of classification and recognition applications. To achieve the needed performance, they include heavy processor operations and memory b...

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Bibliographic Details

Published in:	2023 4th IEEE Global Conference for Advancement in Technology (GCAT) pp. 1 - 6
Main Authors:	Pandey, Jyoti, Asati, Abhijit R., Shenoy, Meetha V., Sikka, Prateek
Format:	Conference Proceeding
Language:	English
Published:	IEEE 06.10.2023
Subjects:	CNN Convolutional neural networks Deep learning Estimation Hardware Hardware design languages Hardware resource utilization High-level synthesis Logic gates MATLAB HDL coder Resource management Systems architecture
Online Access:	Get full text
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